FIMC-IS

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FIMC-IS is an IP block found in Exynos SoCs since Exynos4412/Exynos4212. The FIMC-IS contains various blocks for image processing, along with peripherals for sensor control.

There are several FIMC-IS variants in the wild:

  • FIMC-IS v1.5, in Exynos4x12, which supports 3A, dynamic range compression, and face detection
  • FIMC-IS in Exynos5420, Exynos5410, and Exynos5250, which supports 3A, dynamic range compression, scaling, noise reduction, and image stabilisation.
  • There are more...

FIMC-IS in Exynos4x12

FIMC-IS v1.5 consists of a Cortex-A5 with NEON, 16KB of instruction cache, and 16KB of data cache. It has 2 I2Cs, 2 SPIs, an ADC, UART, MPWM (which provides 6 PWM outputs), 18 GPOs and 18 GPIs for camera sensor control. Camera sensors are connected to FIMC-IS via FIMC-LITE.

FIMC-IS in Exynos4x12 contains three image processing blocks: ISP, DRC (Dynamic Range Compression), and FD (Face Detection). Each block can receive data from DMA, or on-the-fly from the previous block sensor. The ISP block can output either on-the-fly to DRC, or directly to DMA. DRC is incapable of outputting to DMA, and can only output on-the-fly to FIMC and FD. FD does not output image data, so only supports DMA output.

To support communication between the host and the Cortex-A5, FIMC-IS has a MCUCTL block, which provides 64 32-bit registers to communicate with the host, along with registers to control the GPI/GPO pins of FIMC-IS, and registers to send interrupts to and from the A5.